The present invention relates to a data processing unit with a TLB (translation lookaside buffer) for making an address translation from a virtual address to a real address at a high speed, and the present invention further relates to a data processing unit having a TLB purge function.
In a data processing unit (DPU) with a TLB, in order to translate an address from a virtual address to a real address, the real address data is prepared using a segment table and a page table stored in a main memory. The real address data is stored into a TLB. Therefore, subsequent address translation can be carried out by referring to the real address data in the TLB, so long as it is stored therein. In this respect, the addressing can be sped up because there is no need to refer to the various tables in the main memory.
In a computer with a TLB-contained data processing unit of, for example, the multiple virtual storage control type, changing of an executed address space, purging of the entire segment from the main memory, and purging of a certain page assigned to the main memory are frequently required. To this end, the conventional DPU invalidates all of the entries in the TLB, thereby inhibiting the corresponding segment or page from being subsequently accessed. When new TLB entries are prepared for a new executed address space after the address space is changed, the conventional DPU invalidates the new TLB entries. To crepe with this problem, the DPU computes an address and loads the corresponding real address data into the TLB.
In most cases, after the executed space is changed, the main memory of the computer still stores the segment or the page corresponding to the virtual address space, i.e., the address space which is no longer an executed address space as a result of the change in the address space. As described above, all of the entries in the TLB are invalid. If the virtual address space returns to the executed address space and it is necessary to access the segment or the page which originally is not required to be invalidated, the DPU must prepare another real address data again and load it into the TLB, as in the above case. Accordingly, address translation for translating a virtual address into a real address is deteriorated in translation.
To solve this problem, it is necessary to select specific entries from those in the TLB and make them invalid. Such an approach is disclosed in, for example, Japanese Patent Disclosure (Kokai) No. 56-107377, K. Miyazaki et al., Aug. 26, 1981. The Kokai invention refers merely to the fact that, for example, when a page fault occurs, it is desirable to select only the corresponding entries of the TLB and make them invalid. The Kokai invention, however, does not refer to any specific means to do the same. Further, to select the specific entries and make them invalid, it is necessary to specify a segment and a page and to invalidate the TLB entries every time invalidation of the entries is required. This consumes much time and remarkably deteriorates the efficiency of TLB purge processing.